1. Field of the Invention
This invention generally relates to integrated circuit (IC) fabrication and, more particularly, to a method for fabricating a nanowire transistor (NWT).
2. Description of the Related Art
Nanowire transistors (NWTs) are an important technological advancement that enable the fabrication of high-performance devices on substrates that are sensitive to high process temperatures (e.g., glass or plastic). Nanowires can be pre-processed prior to deposition on the substrate in a way that emulates steps used in conventional integrated circuit technology, including the formation of a thermally grown oxide for the gate insulator layer. After the nanowires are coated on a substrate for processing, a conductive gate layer or gate strap layer is deposited and patterned. The conductive layer is etched to reveal the source and drain regions of the device, which are doped via ion implantation to make the regions electrically conductive. The doping can be made either n-type or p-type, depending on the type of device that is desired. Following the doping of the source and drain regions, the material is thermally activated and an interlayer dielectric is deposited over the entire structure. Contact holes are patterned and opened through the interlayer dielectric to reveal the gate/gate strap, source, and drain. A metal layer is deposited and patterned to make electrical contact to the device electrodes.
Silicon (Si) gate straps are often used in the fabrication of nanowire transistor (NWT) architectures. The gate straps provide a means for contacting the outer shell electrode (e.g., TaAlCN outer shell) for core-shell-shell (CSS) nanostructures, or to provide a gate material for core-shell (CS) nanostructures. Due to the fact that the gate material must have a low resistivity, typically an in-situ doped a-Si material is deposited.
FIG. 1 is a cross-sectional view depicting the Si that remains following an anisotropic etching (prior art). In either of the CSS or CS devices, there is concern for any Si that remains following the standard gate etch step. This Si remains due to the fact that the Si is deposited with a highly conformal CVD process and then etched using an anisotropic plasma etch. Due to the cylindrical shape of the nanostructures, the doped Si material remains along the edges of the wires where it is shadowed from the plasma etch process (i.e., at the reentrant corners along the lower/southern hemicylinder of the wires). These reentrant regions, when filled with doped Si, create “stringers” that may inadvertently connect the gate to either the source or the drain. Since these “stringers” can short the device, it is crucial that they be removed.
It would be advantageous if NWT transistors could be formed without conductive reentrant stringers that can inadvertently short the gate electrode to either the drain or source electrodes.